Developed from the article by Daniel Lunsford in TAS, V1. N6. pp 5355
In these opcodes, HX and LX represent the high and loworder bytes of the IX register. HY and LY are analogous for the IY register. The timing for these new IX and IY instructions is 4 Tstates longer than the equivalent H and L instructions.
Also, SLS means Shift Left and Set. This shifts the register left just as an SLA would, and then the LSB is set. The MSB goes into the Carry flag, and sign and parity are adjusted as expected.

Table I Z80 Instructions from 00 through 3F HEX OCT OP AD HEX OCT OP AD 00 000 NOP 01 001 LD BC,nn * 08 010 EX AF,AF' 09 011 ADD HL,BC * 10 020 DJNZ n 11 021 LD DE,nn * 18 030 JR n 19 031 ADD HL,DE 20 040 JR NZ,n 21 041 LD HL,nn * 28 050 JR Z,n 29 051 ADD HL,HL 30 060 JR NC,n 31 061 LD SP,nn * 38 070 JR C,n 39 071 ADD HL,SP 02 002 LD (BC),A 03 003 INC BC 0A 012 LD A,(BC) 0B 013 DEC BC 12 022 LD (DE),A 13 023 INC DE 1A 032 LD A,(DE) 1B 033 DEC DE 22 042 LD (nn),HL 23 043 INC HL 2A 052 LD HL,(nn) 2B 053 DEC HL 32 062 LD (nn),A 33 063 INC SP 3A 072 LD A,(nn) 3B 073 DEC SP 04 004 INC B 05 005 DEC B 0C 014 INC C 0D 015 DEC C 14 024 INC D 15 025 DEC D 1C 034 INC E 1D 035 DEC E 24 0D4 INC H 25 045 DEC H 2C 054 INC L 2D 055 DEC L 34 064 INC (HL) 35 065 DEC (HL) 3C 074 INC A 3D 075 DEC A 06 006 LD B,n 07 007 RLCA 0E 016 LD C,n 0F 017 RRCA 16 026 LD D,n 17 027 RLA 1E 036 LD E,n 1F 037 RRA 26 046 LD H,n 27 047 DAA 2E 056 LD L,n 2F 057 CPL 36 066 LD (HL),n 37 067 SCF 3E 076 LD A,n 3F 077 CCF Table II Z80 Instructions from 40 through 7F 8Bit Interregister Transfers General form: OCT OP AD 1(r1)(r2) LD REG(r1),REG(r2) Source is REG(r2), destination is REG(r1), where r1 and r2 are 8bit registers (see Table VI). HEX OCT OP AD HEX OCT OP AD 40 100 LD B,B 41 101 LD B,C 48 110 LD C,B 49 111 LD C,C 50 120 LD D,B 51 121 LD D,C 58 130 LD E,B 59 131 LD E,C 60 140 LD H,B 61 141 LD H,C 68 150 LD L,B 69 151 LD L,C 70 160 LD (HL),B 71 161 LD (HL),C 78 170 LD A,B 79 171 ADD A,C 42 102 LD B,D 43 103 LD B,E 4A 112 LD C,D 4B 113 LD C,E 52 122 LD D,D 53 123 LD D,E 5A 132 LD E,D 5B 133 LD E,E 62 142 LD H,D 63 143 LD H,E 6A 152 LD L,D 6B 153 LD L,E 72 162 LD (HL),D 73 163 LD (HL),E 7A 172 LD A,D 7B 173 LD A,E 44 104 LD B,H 45 105 LD B,L 4C 114 LD C,H 4D 115 LD C,L 54 124 LD D,H 55 125 LD D,L 5C 134 LD E,H 5D 135 LD E,L 64 144 LD H,H 65 145 LD H,L 6C 154 LD L,H 6D 155 LD L,L 74 164 LD (HL),H 75 165 LD (HL),L 7C 174 LD A,H 7D 175 LD A,L 46 106 LD B,(HL) 47 107 LD B,A 4E 116 LD C,(HL) 4F 117 LD C,A 56 126 LD D,(HL) 57 127 LD D,A 5E 136 LD E,(HL) 5F 137 LD E,A 66 146 LD H,(HL) 67 147 LD H,A 6E 156 LD L,(HL) 6F 157 LD L,A 76 166 HALT 77 167 LD (HL),A 7E 176 LD A,(HL) 7F 177 LD A,A Table III Z80 Instructions from 80 through BF 8Bit Arithmetic and Logic General form: OCT OP AD 2(op3)(r) OP(op3) [A,]REG(r) The [A,] field is used with ADD, ADC and SBC to avoid ambiguity with other instructions. For the operation codes OP(op3) and the 8bit register codes see Table VI. HEX OCT OP AD HEX OCT OP AD 80 200 ADD A,B 81 201 ADD A,C 88 210 ADC A,B 89 211 ADC A,C 90 220 SUB B 91 221 SUB C 98 230 SBC A,B 99 231 SBC A,C A0 240 AND B A1 241 AND C A8 250 XOR B A9 251 XOR C B0 260 OR B B1 261 OR C B8 270 CP B B9 271 CP C 82 202 ADD A,D 83 203 ADD A,E 8A 212 ADC A,D 8B 213 ADC A,E 92 222 SUB D 93 223 SUB E 9A 232 SBC A,D 9B 233 SBC A,E A2 242 AND D A3 243 AND E AA 252 XOR D AB 253 XOR E B2 262 OR D B3 263 OR E BA 272 CP D BB 273 CP E 84 204 ADD A,H 85 205 ADD A,L 8C 214 ADC A,H 8D 215 ADC A,L 94 224 SUB H 95 225 SUB L 9C 234 SBC A,H 9D 235 SBC A,L A4 244 AND H A5 245 AND L AC 254 XOR H AD 255 XOR L B4 264 OR H B5 265 OR L BC 274 CP H BD 275 CP L 86 206 ADD A,(HL) 87 207 ADD A,A 8E 216 ADC A,(HL) 8F 217 ADC A,A 96 226 SUB (HL) 97 227 SUB A 9E 236 SBC A,(HL) 9F 237 SBC A,A A6 246 AND (HL) A7 247 AND A AE 256 XOR (HL) AF 257 XOR A B6 266 OR (HL) B7 267 OR A BE 276 CP (HL) BF 277 CP A Table IV Z80 Instructions from C0 through FF HEX OCT OP AD HEX OCT OP AD C0 300 RET NZ C1 301 POP BC C8 310 RET Z C9 311 RET D0 320 RET NC D1 321 POP DE D8 330 RET C * D9 331 EXX E0 340 RET PO E1 341 POP HL E8 350 RET PE E9 351 JP (HL) F0 360 RET P F1 361 POP AF F8 370 RET M F9 371 LD SP,HL C2 302 JP NZ,nn C3 303 JP nn CA 312 JP Z,nn * CB 313 (See notes) D2 322 JP NC,nn D3 323 OUT n,A DA 332 JP C,nn DB 333 IN A,n E2 342 JP PO,nn E3 343 EX (SP),HL EA 352 JP PE,nn EB 353 EX DE,HL F2 362 JP P,nn F3 363 DI FA 372 JP M,nn FB 373 EI C4 304 CALL NZ,nn C5 305 PUSH BC CC 314 CALL Z,nn CD 315 CALL nn D4 324 CALL NC,nn D5 325 PUSH DE DC 334 CALL C,nn * DD 335 (See notes) E4 344 CALL PO,nn E5 345 PUSH HL EC 354 CALL PE,nn * ED 355 (See notes) F4 364 CALL P,nn F5 365 PUSH AF FC 374 CALL M,nn * FD 375 (See notes) C6 306 ADD A,n C7 307 RST 00H CE 316 ADC A,n CF 317 RST 08H D6 326 SUB n D7 327 RST 10H DE 336 SBC A,n DF 337 RST 18H E6 346 AND n E7 347 RST 20H EE 356 XOR n EF 357 RST 28H F6 366 OR n F7 367 RST 30H FE 376 CP n FF 377 RST 38H Table V Extended Z80 Instructions Prefixed by ED Listed by Second Byte HEX OCT OP AD HEX OCT OP AD 40 100 IN B,(C) 41 101 OUT (C),B 48 110 IN C,(C) 49 111 OUT (C),C 50 120 IN D,(C) 51 121 OUT (C),D 58 130 IN E,(C) 59 131 OUT (C),E 60 140 IN H,(C) 61 141 OUT (C),H 68 150 IN L,(C) 69 151 OUT (C),L 70 160 (NONE) 71 161 (NONE) 78 170 IN A,(C) 79 171 OUT (C),A 42 102 SBC HL,BC 43 103 LD (nn),BC 4A 112 ADC HL,BC 4B 113 LD BC,(nn) 52 122 SBC HL,DE 53 123 LD (nn),DE 5A 132 ADC HL,DE 5B 133 LD DE,(nn) 62 142 SBC HL,HL 63 143 (NONE, see 22H) 6A 152 ADC HL,HL 6B 153 (NONE, see 2AH) 72 162 SBC HL,SP 73 163 LD (nn),SP 7A 172 ADC HL,SP 7B 173 LD SP,(nn) 44 104 NEG 45 105 RETN 4C 114 (NONE) 4D 115 RETI 46 106 IM 0 47 107 LD I,A 4E 116 (NONE) 4F 117 LD R,A 56 126 IM 1 57 127 LD A,I 5E 136 IM 2 5F 137 LD A,R 66 146 (NONE) 67 147 RRD 6E 156 (NONE) 6F 157 RLD A0 240 LDI A1 241 CPI A8 250 LDD A9 251 CPD B0 260 LDIR B1 261 CPIR B8 270 LDDR B9 271 CPDR A2 242 INI A3 243 OUTI AA 252 IND AB 253 OUTD B2 262 INIR B3 263 OTIR BA 272 INDR BB 273 OTDR Table VI Extended Z80 Instructions Prefixed by CB Listed by Second Byte OCT OP AD p OP(p) 0(p)(r) OP(p) REG(r) 0 RLC 1(n)(r) BIT n,REG(r) 1 RRC 2(n)(r) RES n,REG(r) 2 RL 3(n)(r) SET n,REG(r) 3 RR 4 SLA 5 SRA 6 SLO (See notes) 7 SRL Other octal fields common in Z80 instructions 8Bit Registers: r 0 1 2 3 4 5 6 7 REG(r) B C D E H L (HL) A 16 Bit Registers: R 0 1 2 3 REG(R) BC DE HL SP Operations (see Table I): op1 0 1 2 3 4 5 6 7 OP(op1) JR LD/ADD LD INC/DEC INC DEC LD rotate OP(1) and OP(3) are 16bit instructions, OP(6) are the immediate loads. OP(2) is 4 8bit indexed memory, 2 16bit and 2 8bit memeory loads. OP(7) includes 4 rotates of A, DAA, CPL, SCF and CCF. Operations (see Table III): op3 0 1 2 3 4 5 6 7 OP(op3) ADD ADC SUB SBC AND XOR OR CP Operations (see Table IV): op4 0 1 2 3 4 5 6 7 OP(op4) RET CN(c)  JP CN(c),nn  CALL CN(c),nn PUSH op3 RST OP(5) includes the unconditional CALL plus the prefixes DD, FD, and ED OP(6) is the immediate 8bit arithmetic and logical operations ADD A,n etc. Conditions for JR, JP, CALL, RET c 0 1 2 3 4 5 6 7 CN(c) NZ Z NC C PO PE P M JR implements only the first four 
Notes:
(1)  Instructions in the Z80 but not in the 8080 instruction set are marked with an asterisk preceeding the hex instruction in Tables I through IV. None of the instructions in Tables V and VI are in the 8080 instruction set. None of the instructions involving the auxiliary index registers IX and IY are in the 8080 instruction set. 
(2)  The byte CB indicates the first byte of the extended Z80 instructions given in Table V. 
(3)  The bytes DD and FD are used to prefix instructions using the auxiliary index registers IX and IY. In singlebyte instructions, using memory location (HL), the memory location pointed to m, where m is (IX+d) or (IY+d), may be substituted for (HL) by prefixing the instruction by DD or FD, respectively, and spcifying (HL) as the source or destination in the instruction format. The instruction is followed by d when this is done and the resulting instruction is 3 bytes long. 
(4)  The byte ED indicates the first byte of the extended Z80 instructions given in Table VI. 
(5)  Prefixing singlebyte 8bit instructions involving registers H and L by DD (for IX) or FD (for IY) results in use of XH, XL, YH or YL instead. This usage is undocumented and works only on Zilog Z80’s and secondsources which use Zilog masks. XH, XL, YH and YL refer to the highorder bytes of IX and IY, respectively. ALDS supports these instructions. 
(6)  The SLO operation in Table V is undocumented and is not well defined. 
(7)  All the instructions in Table V can be extended to undocumented Zilog Z80 instructions: These instructions, which use (IX+d) and (IY+d) as the source and destination as well as load the result in r, result when the (IX+d) or (IY+d) format is used and registers other than (HL) are specified. The resulting instrucions are 4 bytes long. ALDS supports these instructions using the format [OP]LD r,m where m is (IX+d) or (IY+d). The timing is the same as [OP] m. 